1. Field of the Invention
The present invention is directed to methods for preparing SiO.sub.2 layers in semiconductor devices by the rapid thermal oxidation of silicon in an ozone ambient.
2. State of the Art
Integrated circuit fabrication requires the formation of numerous circuit elements (e.g., transistors such as MOS transistors in very large scale integration devices) on the surface of a silicon substrate and subsequent connection of some of these elements. Such fabrication requires the formation of numerous SiO.sub.2 layers in semiconductor devices, including formation of SiO.sub.2 gate oxide layers, SiO.sub.2 dielectric (insulating) layers, etc.
For example and as shown in FIGS. 1 and 2, transistor elements, such as transistor element 2, are found on surface of substrate 1. Substrate 1 is part of a silicon wafer which has been processed by conventional techniques to produce a plurality of individual dies or chips. In general, the entire wafer will be subject to the processing steps which are described hereinafter. The drawing, however, illustrates only a small portion of the wafer substrate.
Further in this regard, transistor element 2 generally contains a source site 3 and a reciprocal drain site 4 which are connected by channel 5. In some cases, as shown by FIG. 2, the transistor element 2 is contained within a well region 9. The latter situation is well-known in the art for CMOS transistor fabrication. The substrate I, source site 3, drain site 4, channel 5, and well region 9 are typically doped with Group III element(s) (P-type) such as boron or with Group V element(s) (N-type) such as phosphorus, arsenic, antimony, and the like. Typically, the dopants for substrate 1 (or well region 9, if employed) are different in type as compared to that for source site 3 and drain site 4 (e.g., if substrate 1 employs a P-type dopant, then source site 3 and drain site 4 will use an N-type dopant). The dopant in the source 3 and drain 4 sites serves, in part, to electrically isolate the source 3 and drain 4 sites from the substrate 1 (or well region 9, if employed); and to provide an electrically conductive path to the channel region 5. The dopant in the channel 5 is chosen, in part, to determine the desired voltage threshold (i.e., turn-on or turn-off voltage) of the transistor 2.
In transistor element 2, silicon dioxide (SiO.sub.2) layer 6 is deposited or grown on the surface of substrate 1 over channel 5, or the region which will become channel 5. SiO.sub.2 layer 6 serves as a "gate oxide" to electrically isolate the gate 7 from the channel 5. One method for forming SiO.sub.2 layer 6 onto substrate 1 is by the furnace oxidation of silicon in either a oxygen or ozone ambient at high temperatures (i.e., &gt;800.degree. C.). However, when silicon is heated to a high temperature for extended periods of times, dopants in the silicon can migrate and create problems in the fabrication of active devices.
Specifically, in very large scale integration ("VLSI") and other semiconductor devices, the regions of dopant in silicon wafer are precisely controlled. Thermal treatments, however, can cause the dopants to diffuse and thereby reduce the control of their concentration and locations. For devices fabricated with feature sizes below about 2.0 .mu.m (e.g., in a 0.25-2.0 .mu.m range), dopant diffusion (both vertically and horizontally) must be reduced to maintain shallow junctions, controlled gate lengths, etc. Contrarily, when SiO.sub.2 layer 6 is formed by thermal (furnace) oxidation, dopant diffusion in channel 5 is difficult to control because the large thermal mass of the susceptors, wafer boats, and reactor walls in the furnace requires that such oxidation be conducted at elevated temperatures for extended periods of time. Similarly, if dopants are introduced to form source site 3 and its reciprocal drain site prior to the formation of SiO.sub.2 layer 6, dopant diffusion of the source 3 and drain 4 sites is also difficult to control during such thermal oxidation.
In view of the above, the maximum acceptable amount of dopant diffusion in the device during oxidation of the silicon to silicon oxide is often referred to as a "thermal budget" which amount is both temperature and time dependent. Specifically, at a given temperature, there is a maximum time (or the maximum temperature for a given time) permitted to form a SiO.sub.2 layer 6 to a required depth and within permissible levels of dopant migration. As this temperature is lowered, the oxidation can proceed for a longer period of time without exceeding the maximum acceptable amount of dopant diffusion.
With all other factors being equal, the specific thermal budget which can be employed is a variable which is directly related to the amount of dopant migration which can be tolerated in a given semiconductor process technology. In turn, the level of tolerable dopant migration depends, in part, on the short channel transistor performance. Specifically, short channel transistor performance characteristics are negatively impacted when dopant migration exceeds defined levels.
In order to reduce thermal budget and, accordingly, minimize loss of short channel transistor performance, rapid thermal oxidation ("RTO") in an oxygen ambient has been employed. While this procedure results in a significant reductions in thermal budget as compared to furnace oxidation, the continued decrease in feature sizes associated with an increase in the number of circuit elements per chip requires an even lower thermal budget.